Recently, the performance of processors included in mobile devices such as smartphones is rapidly improving. The high-performance processors for mobile applications have a significant problem in that the battery run time is short. Therefore, not only the performance of the processors but also the power consumption thereof is important. A study on the use of nonvolatile memories such as spin transfer torque magnetic random access memories (STT-MRAMs) as cache memories for the processors is recently attracting attention as a technique for reducing power consumption of the processors. Unlike volatile memories such as SRAMs, nonvolatile memories can hold data even if no power is supplied. Accordingly, nonvolatile memories are expected to reduce standby power.
However, nonvolatile memories generally have a problem in that power consumption during operation is great. For this reason, although various ideas for using nonvolatile memories as cache memories have been made public, no high-performance processor actually using nonvolatile memories as cache memories has been commercially available. Furthermore, no nonvolatile memory has been made available, which meets the operational speed and the operational power requirements of high-performance processors.
It is known that all bit lines in a memory are pre-charged or pre-discharged before a next cycle starts in order to avoid a half select state of memory cells connected to a word line. However, as will be described later, the power consumed for pre-charging or pre-discharging is not essentially required for memory operation, but needed only to avoid malfunctions. Furthermore, the power needed to charge or discharge bit line pairs is for pre-charging or pre-discharging all the bit line pairs after a read or write operation, and is superfluous.